High Speed USB in a Two Layer PCB

Every so often we get asked to design a “simple” PCB that isn’t simple, and a high-speed USB interposer PCB we did recently is a good example. Basically all it was meant to do was carry D+, D-, +5V, and ground from a set of USB lines on a “pogo” style industrial connector out to a pigtail of wires to an end device. And since there were only a total of four nets in the entire board (five, if you count an enable line that got tied directly to ground), it seemed perfectly reasonable to put them all on a two layer board. But sometimes things are nowhere near as simple as they first appear, and this was such a case.

The catch here is that with USB2.0, impedances are critical.  In particular, the D+ to D- impedance must be 90 ohms and the impedance of either line to ground must be 30 ohms.  If this specification is significantly violated, reflections result, and it becomes difficult for the PLL that recovers the USB clock to lock on and stay locked.  At low and full speeds (1.5 Mbps and 12 Mbps, respectively), the situation isn’t quite so perilous.  But with high-speed USB connections, a fifth harmonic, which can be important in clock recovery, is up at 2.4GHz.  Additionally, not all host controller chips and their operating system drivers fail gracefully when the USB “chirping” process is mangled by a messy signal waveform.  Some will simply shut down the endpoint rather than continue to interact at USB1.1 speed

USB Layout Guidelines, Courtesy Intel Corp.

In part for this reason, most USB circuit boards are of at least four layers in order to keep the data lines physically close to a ground plane below them.  The more layers there are in a PCB, the thinner the fiberglass between copper layers can be made — thus keeping the overall dielectric down to where the characteristicimpedance to ground can be as low as 30 ohms.  In practice, boards with USB endpoint controllers or hubs on them are usually electrically complex enough that they’ve got at least four layers in them, anyway, so the imposition of a requirement to put a ground plane just one plane below the D+/D- signal layer is no big deal.  And the 90 ohm differential impedance between D+ and D- is usually easy to guarantee in any number of layers, since D+ and D- are generally routed on an outside (or at least the same) layer.   All that’s required is that the spacing between the traces and their widths be selected correctly to get the (self-inductive) “L” and (trace to trace) “C” required to satisfy the 90 ohm requirement.
When you’re limited to two layers, however, satisfying the 30 ohm impedance to ground requirement gets a lot more difficult.  The reason for this is that you’ve probably got your data lines on the top side of the PCB, a ground plane on the bottom, and 0.062″ of fiberglass between them.  With that much fiberglass dielectric between signal traces and ground (and capacitance falling off as 1/distance), signal traces have to become large to compensate.  To put things in perspective, what would be D+/D- lines at 5mil trace and 5mil space in a four layer board become 18mils wide with 6mil spacing in a two-layer board.  And depending on what kind of connector is used (and its pin density), that might not even be routable.

CPWG routing example, courtesy www.microwaves101.com

A solution is to use “Co-Planar Waveguide” (CPWG) routing, which is most commonly thought of as a microwave routing technique.  Here in the case of USB you’d insert copper for a ground between the data lines to provide additional capacitance to drive down the overall effective characteristic impedance by increasing capacitance to ground of those signals.  For the case of USB2.0 (480Mbps) on a two-layer PCB, use of CPWG routing can drop line widths from 18mils to 12mils (with spacing remaining at 6mils), which may well be what’s required to keep the board routable.

Remember with all this advice, you’re looking to match impedances all down the transmission line to assure that you don’t get back reflections of signals, since it’s those back reflections that can move the zero crossing points of the data waveform, thus skewing duty cycles and making PLL clock recovery impossible.

Once you’ve got inbound data reclocked on a local clock (through PLL recovery), you’re home free.  But until that point, thinking through the physical implications of PCB layout can make the difference between a USB device that runs at USB2.0 speed properly, one that won’t ever get above 12Mbps because the chirping process won’t complete, or one that the operating system decides to shut down entirely.


(And while we’re on the subject, it’s probably worth mentioning that we have a simple example OrCAD schematic that shows the techniques we often use when developing PCB’s.)

About overton

CEO of Focus Embedded with 20+ years of engineering design experience.
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